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MCM64PC32T ? mcm64pc64t 1 motorola fast sram advance information 256k/512k pipelined burstram ? secondary cache module for pentium ? the MCM64PC32T (256k) and mcm64pc64t (512k) are designed to pro- vide a burstable, high performance, l2 cache for the pentium microprocessor in conjunction with intel's triton ii chip set. the MCM64PC32T is configured as 32k x 64 bits and the mcm64pc64t is configured as 64k x 64 bits. both are pack- aged in a 160 pin card edge memory module. each module uses motorola's 3.3 v 32k x 32 burstrams and one motorola 3.3 v 32k x 8 fsram for the tag ram. bursts can be initiated with either address status processor (adsp ) or cache address status (cads ). subsequent burst addresses are generated internal to the burstram by the cache burst advance (cadv ) input pin. write cycles are internally self timed and are initiated by the rising edge of the clock (clk0) input. eight write enables are provided for byte write control. pd0 pd3 map into the triton ii chip set for autoconfiguration of the cache control. ? pentiumstyle burst counter on chip ? pipelined data out ? 160 pin card edge module ? address pipeline supported by adsp disabled with e x ? all cache data and tag i/os are ttl compatible ? three state outputs ? byte write capability ? fast module clock rate: 66 mhz ? fast sram access times:15 ns for tag ram 8 ns for data rams ? 1.5 cycle deselect data rams ? decoupling capacitors for each fast static ram ? high quality multilayer fr4 pwb with separate power and ground planes ? single 3.3 v +10%, 5% power supply ? burndy connector, part number: celp2x80sc3z48 ? intel coast 3.0 option iii compliant ? burst order select (bosel) option burstram is a trademark of motorola. pentium is a trademark of intel corp. this document contains information on a new product. specifications and information herein are subject to change without notice. semiconductor technical data order this document by MCM64PC32T/d MCM64PC32T mcm64pc64t 160lead card edge case tbd, top view 80 43 42 1 1/22/97 ? motorola, inc. 1997
MCM64PC32T ? mcm64pc64t 2 motorola fast sram bwe cadv adsp cads clk0 cg se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz v dd ccs v dd sa0 sa14 tio0 tio7 twe 15 13 a3 a18 gwe sgw cwe0 cwe3 sba sbd se3 ecs2 ecs1 4.7 k w dq0 dq31 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 15 sgw sba sbd se3 dq32 dq63 cwe4 cwe7 a0 a12 dq0 dq7 a13 w a14 g 32k x 8 e bosel MCM64PC32T block diagram
MCM64PC32T ? mcm64pc64t 3 motorola fast sram bwe cadv adsp cads clk0 cg se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz v dd v dd sa0 sa14 tio0 tio7 twe 13 a3 a17 gwe sgw cwe0 cwe3 sba sbd se3 dq0 dq31 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 15 sgw sba sbd se3 dq32 dq63 cwe4 cwe7 a0 a12 dq0 dq7 a13 w a14 g 32k x 8 e 4.7 k w a18 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 15 sgw sba sbd se3 se1 32k x 32 adv k g sw se2 lbo adsp adsc dq0 dq31 zz sa0 sa14 sgw sba sbd se3 v dd ccs clk1 bosel mcm64pc64t block diagram
pin assignment 160lead card edge module (dimm) top view cwe3 nc nc v ss rsvd a4 a6 a8 a10 v dd 5 a17 v ss a9 a14 a15 rsvd pd0 pd2 bosel v ss clk0 v ss dq63 v dd 5 dq61 dq59 dq57 81 82 83 84 85 86 87 88 89 90 8 9 10 cwe4 cwe6 cwe0 cwe2 v dd 3 ccs gwe bwe v ss a3 a7 a5 a11 a16 v dd 3 a18 v ss a12 a13 adsp ecs1 ecs2 pd1 pd3 v ss clk1 v ss dq62 v dd 3 dq60 dq58 dq56 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 v ss dq55 dq53 dq51 dq49 v ss dq47 dq45 dq43 v dd 5 dq41 dq39 dq37 v ss dq35 dq33 dq31 v dd 5 dq29 dq27 dq25 v ss dq23 dq21 dq19 v dd 5 dq17 dq15 dq13 v ss dq11 dq9 dq7 v dd 5 dq5 dq3 dq1 v ss v ss dq54 dq52 dq50 dq48 v ss dq46 dq44 dq42 v dd 3 dq40 dq38 dq36 v ss dq34 dq32 dq30 v dd 3 dq28 dq26 dq24 v ss dq22 dq20 dq18 v dd 3 dq16 dq14 dq12 v ss dq10 dq8 dq6 v dd 3 dq4 dq2 dq0 v ss v ss tio0 tio2 tio6 tio4 nc v dd 3 twe cads v ss 1 2 3 4 5 6 7 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 v ss tio1 tio7 tio5 tio3 nc v dd 5 nc cadv v ss cg cwe5 cwe7 cwe1 v dd 5 91 92 93 94 95 MCM64PC32T ? mcm64pc64t 4 motorola fast sram presence detect table cache size and functionality pd0 pd1 pd2 pd3 256k pipe burst nc nc v ss nc 512k pipe burst v ss v ss nc v ss
MCM64PC32T ? mcm64pc64t 5 motorola fast sram pin descriptions 160lead card edge pin locations symbol type description 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 a3 a18 input address inputs: these inputs are registered into data rams and must meet setup and hold times. the tag ram addresses are not registered. 30 adsp input address status processor: initiates read, write, or chip deselect cycle (exceptionchip deselect does not occur when adsp is asserted and ccs is high. 114 bosel input burst order select: nc for interleaved burst counter. tie to ground for linear burst counter. 18 bwe input byte write enable: to be used in future modules. 9 cads input cache address status: initiates read, write, or chip deselect cycle. 89 cadv input cache burst advance: increments address count in accordance with interleaved count style. 16 ccs input chip select: active low chip enable for data rams. 91 cg input cache output enable: active low asynchronous input. lowenables output buffers (dq pins) highdqx pins are high impedance. 36, 116 clk0, clk1 input clock: this signal registers the address, data in, and all control signals except cg . 11, 12, 13, 14, 92, 93, 94, 96 cwe0 cwe7 input cache data byte write enable: active low write signal for data rams. 38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51, 53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66, 67, 69, 70, 71, 73, 74, 75, 77, 78, 79, 118, 120, 121, 122, 124, 125, 126, 127, 129, 130, 131, 133, 134, 135, 137, 138, 139, 141, 142, 143, 145, 146, 147, 149, 150, 151, 153, 154, 155, 157, 158, 159 dq0 dq63 i/o synchronous data i/o: drives data out of data rams during read cycles. stores data to data rams during write cycles. 31, 32 ecs1 , ecs2 input expansion chip select 17 gwe input global write enable: to be used in future modules. 33, 34, 112, 113 pd0 pd3 e presence detect: see presence detect table 100, 111 rsvd e no connection: reserved for future use. 2, 3, 4, 5, 82, 83, 84, 85 tio0 tio7 i/o tag ram i/o: drives data out during tag compare cycles. stores data to tag ram during tag write cycles. 8 twe input tag write enable: active low write signal for tag rams. 7, 15, 25, 39, 52, 60, 68, 76 v dd 3 supply power supply: 3.3 v + 10%, 5%. 87, 95, 105, 119, 132, 140, 148, 156 v dd 5 supply power supply: 5.0 v 5%. 1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72, 80, 81, 90, 99, 107, 115, 117, 123, 128, 136, 144, 152, 160 v ss supply ground 6, 86, 88, 97, 98 nc e no connection: there is no connection to the module.
MCM64PC32T ? mcm64pc64t 6 motorola fast sram synchronous truth table (see notes 1, 2, and 3) ccs adsp cads cadv cwex clk0 address used operation h x l x x lh n/a deselected l l x x x lh external address read cycle, begin burst l h l x l lh external address write cycle, begin burst l h l x h lh external address read cycle, begin burst x h h l l lh next address write cycle, continue burst x h h l h lh next address read cycle, continue burst x h h h l lh current address write cycle, suspend burst x h h h h lh current address read cycle, suspend burst h x h l l lh next address write cycle, continue burst h x h l h lh next address read cycle, continue burst h x h h l lh current address write cycle, suspend burst h x h h h lh current address read cycle, suspend burst notes: 1. x means don't care. 2. all inputs except cg must meet setup and hold times for the lowtohigh transition of clock (clk0/1). 3. wait states are inserted by suspending burst. asynchronous truth table (see notes 1 and 2) operation cg i/o status read l data out read h highz write x highz e data in deselected x highz notes: 1. x means don't care. 2. for a write operation following a read operation, g must be high before the input data required setup time and held high through the input data hold time. dc absolute maximum ratings (voltages referenced to v ss = 0 v) rating symbol value unit power supply voltage v dd 3 0.5 to + 4.6 v voltage relative to v ss v in , v out v ss 0.5 to v dd 3 + 0.5 v output current (per i/o) i out 20 ma temperature under bias t bias 10 to + 85 c operating temperature t j 20 to +110 c storage temperature t stg 55 to + 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
MCM64PC32T ? mcm64pc64t 7 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v + 10%, 5%, t j = 20 to + 110 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min max unit notes supply voltage (operating voltage range) v dd 3.135 3.6 v 1 input high voltage v ih 2.0 v dd + 0.3 v 2 input low voltage v il 0.5 0.8 v 3 notes: 1. jedec specification 81a specifies 0.3 v tolerance for v dd . 2. v ih (max) = v dd + 0.3 v dc; v ih (max) = v dd + 1.4 v ac (pulse width 20 ns) for i 20.0 ma. 3. v il (min) = 0.5 v dc; v il (min) = 2.0 v ac (pulse width 20 ns) for i 20.0 ma. dc characteristics parameter symbol min max unit notes input leakage current (all inputs, v in = 0 to v dd 3) i lkg(i) e 1.0 m a output leakage current (cg = v ih ) i lkg(o) e 1.0 m a ttl output low voltage (i ol = + 8.0 ma) v ol e 0.4 v 1 ttl output high voltage (i oh = 4.0 ma) v oh 2.4 e v 1 notes: 1. champing diodes exist to v ss and v dd . power supply currents parameter symbol max unit ac supply current (cg = v ih , ccs = v il , i out = 0 ma, all inputs = v il or v ih , MCM64PC32T v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) mcm64pc64t i dda 495 705 ma ac standby current (cg = v ih , ccs = v il , i out = 0 ma, all inputs = v il or v ih , MCM64PC32T v il = 0.0 v and v ih 3.0 v, cycle time t khkh min) mcm64pc64t i sb1 230 505 ma capacitance (f = 1.0 mhz, dv = 3.0 v, t j = 20 to 110 c, periodically sampled rather than 100% tested) parameter symbol max unit input capacitance MCM64PC32T mcm64pc64t c in 21 31 pf input/output capacitance (dq0 dq63) MCM64PC32T mcm64pc64t c i/o 8 16 pf
MCM64PC32T ? mcm64pc64t 8 motorola fast sram data rams ac operating conditions and characteristics (v dd = 3.3 v + 10%, 5% t j = 20 to + 110 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 2 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 3 unless otherwise noted . . . . . . . . . . . . . . 2.4 input waveform t r test point (unloaded output) output buffer 2.4 0.4 0.4 output waveform output load t f unloaded rise and fall time measurement notes: 1. input waveform should have a slew rate of 1 v/ns. 2. rise time is measure from 0.4 v to 2.4 v unloaded. 3. fall time is measure from 2.4 v to 0.4 v unloaded. figure 1. unloaded rise and fall time characterization
MCM64PC32T ? mcm64pc64t 9 motorola fast sram data rams read/write cycle timing (see notes 1, 2, and 3) MCM64PC32T66 MCM64PC32T66 parameter symbol min max unit notes cycle time t khkh 15 e ns clock access time t khqv e 8 ns 5 output enable to output valid t glqv e 6 ns 5 clock high to output active t khqx1 0 e ns 5, 7 clock high to output change t khqx2 2 e ns 5, 7 output enable to output active t glqx 0 e ns 5, 7 output disable to q highz t ghqz e 8 ns 6, 7 clock high to q highz t khqz 2 8 ns 6, 7 clock high pulse width t khkl 5 e ns clock low pulse width t klkh 5 e ns setup times: address address status data in write address advance chip enable t avkh t adsvkh t dvkh t wvkh t advvkh t evkh 2.5 e ns 4 hold times: address address status data in write address advance chip enable t khax t khadsx t khdx t khwx t khadvx t khex 0.5 e ns 4 notes: 1. write applies to all sbx , sw , and sgw signals when the chip is selected and adsp high. 2. chip enable applies to all se1 , se2 and se3 signals whenever adsp or adsc is asserted. 3. all read and write cycle timings are referenced from k or g . 4. g is a don't care after write cycle begins. to prevent bus contention, g should be negated prior to start of write cycle. 5. tested per ac test load. 6. measured at 200 mv from steady state. tested per highz test load. 7. this parameter is sampled and is not 100% tested.
MCM64PC32T ? mcm64pc64t 10 motorola fast sram test point 3.6 3.135 2.8 1.65 1.4 0 0 40 120 test point v dd 1.65 1.8 0.3 0 0 46 120 current (ma) current (ma) voltage (v) voltage (v) voltage (v) pullup i (ma) min i (ma) max 0.5 0 1.4 1.65 2 3.135 3.6 40 40 40 37 28 0 0 120 120 120 104 81 20 0 voltage (v) pulldown i (ma) min i (ma) max 0.5 0 0.5 1 1.65 1.8 3.6 4 34 0 17 35 45 46 46 46 126 0 47 90 114 120 120 120 2a. pullup 2b. pulldown 5 5 80 dc drive point ac drive point ac drive point dc drive point 80 notes: 1. driver impedance @ 1.65 v = 15.9 to 44.6 w . 2. meets the temperature and voltage range specified in dc characteristics tables. 3. this drawing is not to scale. comparisons should be made to the table in figure 2a. notes: 1. driver impedance @ 1.65 v = 15.9 to 44.6 w . 2. meets the temperature and voltage range specified in dc characteristics tables. 3. this drawing is not to scale. comparisons should be made to the table in figure 2b. figure 2. output buffer characteristics
MCM64PC32T ? mcm64pc64t 11 motorola fast sram burst read single read cads t khkl t khkh dqx esc1 clk0, clk1 adsp cadv q(a) burst write adsp, ax ax ab data rams read/write cycles t klkh cd ccs w q(b) q(b+1) t khqv burst wraps around q(b+2) q(b+3) q(b) d(c) d(c+1) d(c+2) d(c+3) q(d) t khqv deselected single read esc1 ignored cg t khqx1 t khqx2 t ghqz t glqx note: w low = gwe low and/or bwe and cwex low. q(n1) (address) t khqz t klqz
MCM64PC32T ? mcm64pc64t 12 motorola fast sram tag ram ac operating conditions and characteristics (v dd = 3.3 v 0.3 v, t j = 20 to + 110 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing measurement reference level 1.5 v . . . . . . . . . . . . . output load figure 3 unless otherwise noted . . . . . . . . . . . . . . . . . . tag ram read cycle (see notes 1 and 2) 15 parameter symbol min max unit notes read cycle time t avav 15 e ns 3 address access time t avqv e 15 ns output hold from address change t axqx 4 e ns 4, 5 notes: 1. cwe is high for read cycle. 2. device is continuously selected (cg = v il ). 3. all timings are referenced from the last valid address to the first address transition. 4. transition is measured 500 mv from steadystate voltage with load of figure 3b. 5. this parameter is sampled and not 100% tested. tag ram read cycle (see note 5) q (data out) ax (address) data valid previous data valid t avav t axqx t avqv output z 0 = 50 w 50 w v l = 1.5 v (a) (b) 5 pf 3.3 v output 351 w 317 w timing limits the table of timing values shows either a minimum or a maximum limit for each param- eter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time. on the other hand, responses from the memory are specified from the de- vice point of view. thus, the access time is shown as a maximum since the device never provides data later than that time. figure 3. test loads
MCM64PC32T ? mcm64pc64t 13 motorola fast sram tag ram write cycle (see notes 1 and 2) 15 parameter symbol min max unit notes write cycle time t avav 15 e ns 3 address setup time t avwl 0 e ns address valid to end of write t avwh 12 e ns data valid to end of write t dvwh 7 e ns data hold time t whdx 0 e ns write low to output highz t wlqz 0 7 ns 5,6,7 write high to output active t whqx 4 e ns 5,6,7 write recovery time t whax 0 e ns notes: 1. a write occurs when cwe is low. 2. if cg goes low coincident with or after cwe goes low, the output will remain in a high impedance state. 3. all timings are referenced from the last valid address to the first address transition. 4. if cg v ih , the output will remain in a high impedance state. 5. at any given voltage and temperature, t wlqz (max) is less than t whqx (min), both for a given device and from device to device. 6. transition is measured 500 mv from steadystate voltage with load of figure 3b. 7. this parameter is sampled and not 100% tested. tag ram write cycle (see notes 1 and 2) data valid t dvwh t avwl t avwh t avav t whax t wlwh t whdx t wlqz t whqx high z high z ax (address) twe q (data out) d (data in)
MCM64PC32T ? mcm64pc64t 14 motorola fast sram ordering information (order by full part number) 64pc32t mcm 64pc64t xx xx motorola memory prefix part number full part number e MCM64PC32Tsg66 mcm64pc64tsg66 speed (66 = 66 mhz) package (sg = gold pad simm)
MCM64PC32T ? mcm64pc64t 15 motorola fast sram package dimensions 160lead card edge module case tbd m p (n) a side view e l k r 160x h 160x r w d 160x 156x y l 0.004 (0.1) x s t dim min max min max millimeters inches a 4.330 4.350 109.98 110.49 b 1.120 1.140 28.45 28.96 c 0.454 11.53 d 0.033 0.037 0.84 0.94 e 2.265 2.275 57.53 57.79 f 0.075 bsc 1.91 bsc g 0.050 bsc 1.27 bsc h 0.030 0.51 j 0.055 0.069 1.40 1.75 k 0.210 5.33 l 1.955 1.965 49.66 49.91 m 2.155 2.165 54.74 54.99 n 0.110 ref 2.79 ref p 0.300 7.62 r 0.492 0.512 7.24 7.75 v 0.300 7.62 w 0.040 0.060 1.02 1.52 ab 0.262 6.66 ac 0.072 0.076 1.83 1.93 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. card thickness applies across tabs and includes plating and/or metallization. 4. dimensions c and v define a doublesided module. 5. dimension ab defines optional singlesided module. 6. straightness callout applies to tab area only. g 2x back view component view aa ac f x y b view aa min .285 inches, component 80 43 42 1 area front view v note 4 ab note 5 j note 6 m 0.012 (0.3) t area 160 123 122 81 c note 4 note: case outline number to be determined. max .305 inches
MCM64PC32T ? mcm64pc64t 16 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado, 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com e touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MCM64PC32T/d ?

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